Technical Field
The present invention relates to testing integrated circuits (ICs) for final test area. More specifically, the invention relates to a process for efficient testing of ICs through successive testing with embedded segregation.
Background
An integrated circuit, hereinafter referred to as an IC, is a small electronic device made out of a semi-conductor wafer. IC testing is integral to the process of manufacturing ICs to ensure that the ICs meet quality control standards. Manufacturing of ICs is in itself a time sensitive process. Similarly, testing of ICs is also time consuming.
Different testing protocols have been employed to reduce a cycle time for testing ICs. While some of these protocols reduce testing time, there are aspects of IC testing that are negatively affected, including, but not limited to, deterioration in test intensiveness. Time is a factor in IC testing, but it is not the sole factor. Prior art solutions that reduce time for IC testing have been affected with test coverage issues and a decrease in product reliability. Implementing hardware or software upgrades may also reduce testing cycle time. However, such upgrades involve a cost as it requires replacement of existing hardware or software resources or fabricating additional hardware or software. In addition, any hardware or software upgrade may also require longer implementation time. Accordingly, prior art solutions pertaining to test time reduction and hardware or software upgrades have compromised testing cost and/or product reliability.